§ Vivado toolchain craziness


I found this file as I was cleaning up some old code, for a project to implement a fast K/V store on an FPGA , so I thought I should put this up for anyone else who stumbles on the same frustrations / errors. I'm not touching this particular toolchain again with a 10-foot pole till the tools stabilize by a lot .

§ Vivado HLS issues



[BD 41-241] Message from IP propagation TCL of /blk_mem_gen_7: set_property
error: Validation failed for parameter 'Write Width A(Write_Width_A)' for BD
Cell 'blk_mem_gen_7'. Value '8' is out of the range (32,1024) Customization
errors found on 'blk_mem_gen_7'. Restoring to previous valid configuration.


struct S {
    bool b;
    int16 x;
    int16 y;
}

This gets generated as 3 ports for memory, of widths 1, 16, 16. Ideally, I wanted one port, of width 16+16+1=33, for each struct value. However, what was generated were three ports of widths 1, 16, and 16 which I cannot connect to BRAM.


struct Foo {...};
void f (Foo conflict) {
    #pragma HLS interface bram port=conflict
}

void g (Foo conflict) {
    #pragma HLS interface bram port=conflict
}


// HLS side
struct Vec2  { int x; int y};
void f(Vec2 points[NUM_POINTS]) {
	#pragma HLS DATA_PACK variable=points
    #pragma HLS INTERFACE bram port=points

    points[0] = {2, 3};
}

// Host side
Vec2 *points = (Vec2 *)(0xPOINTER_LOCATION_FROM_VIVADO);

int main() {
    // points[0] will *not* be {2, 3}!
}



§ SDAccel bugs


link to tutorial we were following
zynq> /hashing.elf
/hashing.elf: error while loading shared libraries:
libxilinxopencl.so: cannot open shared object file: No such file or directory

At this point, clearly we have some linker issues (why does xocc not correctly statically link? What's up with it? Why does it expect it to be able to load a shared library? WTF is happening ). do note that this is not the way the process is supposed to go according to the tutorial!

At some point, I gave up on the entire enterprise.